A prior art synchronous counter flip flop circuit 10 is illustrated in the simplified logic circuit diagram of FIG. 1. A logical AND input circuit 12 has a plurality of inputs 14 including count logic signal inputs BIT0-BIT7 and a count enable clock signal input CET. The logical AND input circuit 12 provides a first output 15 delivering a first count signal upon concurrence of count logic signals at the count logic signal inputs BIT0-BIT7 with a count enable clock signal at the count enable clock signal input CET during a clock cycle. In the example of FIG. 1 using positive AND logic, concurrence of logic high potential level count logic signals with a logic high potential level count enable clock signal at the inputs 14 produces a logic high potential level first count signal at the first output 15.
An inverting output buffer circuit 16 is coupled to the first output 15 and provides a final terminal count output 18. The terminal count flip flop circuit operates by "decoding" the logic signal values of logic signals at the respective inputs 14. When all of the input signals at the inputs 14 are at logic high potential level, the device is in the terminal count condition and provides an intermediate terminal count signal TC of logic high potential level at the input of output buffer 16. The output buffer 16 provides the inverted terminal count signal TC at the terminal count output 18. The final terminal count signal TC is typically coupled to activate further cascaded counters generating, for example, more significant bits of a count total.
Two example prior art circuit implementations of the generalized logic circuit diagram of FIG. 1 are illustrated in FIGS. 2 and 3. In both examples, the inverting output buffer circuit 16 is a conventional inverting TTL output buffer circuit having a pullup transistor element Darlington transistor pair Q4,Q5, pulldown transistor element Q3 and a phase splitter transistor element Q2 coupled to control the conducting states of the pullup and pulldown transistor elements in opposite phase. In the example of FIG. 2 the logical AND input circuit 12 is provided by coupling the respective inputs 14 in parallel to the base node BPS of the phase splitter transistor element Q2. The parallel coupled inputs 14 provide an effective AND gate input circuit coupling delivering an intermediate terminal count signal TC, at the first output 15 and base node BPS of Q2, in the terminal count condition. The inverting output buffer 16 provides the final terminal count signal TC at the final terminal count output 18.
In the example of FIG. 3 the logical AND input circuit 12 is provided by a multiemitter transistor element QME1. The multiple emitters of QME1 are coupled respectively to the multiple inputs 14. The base node of QME1 is coupled to the high potential level power rail V.sub.cc through base resistor R3 while the collector node provides the first output 15 coupled to the base node BPS of phase splitter transistor element Q2.
A disadvantage of the conventional circuit implementations illustrated in FIGS. 2 and 3 is that unavoidable opposite edge skew of internal logic signals, and bit to bit variation of the internal logic signals may cause fortuitous and transient duration concurrence of high potential level conditions at the respective inputs 14. Such transient concurrent conditions or race conditions may cause unwanted low potential level noise spikes at the final terminal count output 18. Such noise spikes are referred to as decoding spikes. The probability of occurrence of decoding spikes increases in high speed TTL logic families which have the least propagation delay through the inverting output buffer circuit. These decoding noise spikes make the final terminal count output 18 unsuitable for driving edge triggered or a synchronous inputs and the final inverted terminal count signal TC is unsuitable for use as a clock signal or reset signal.